The present invention relates to an electronic digital circuit, and more particularly to a circuit for synchronizing high frequency, asynchronous data.
Most electronic data processing systems, at one point or another, must receive and assimilate asynchronous data signals, such as the signals from keyboard inputs, or asynchronous serial data ports. One known data synchronizer uses a type of AND gate to sample the asynchronous data at a data input with an edge (either leading or trailing) of a clock pulse. Each sample is, therefore, the binary product of the asynchronous input signal level and the clock edge level. Further, each binary product is subsequently stored in a flip-flop, until it is synchronously read by the remainder of the receiving system.
A common problem with this known type of data synchronizer is metastable oscillation which occurs in flip-flops and similar cross coupled devices when the asynchronous input signal is changing binary states at the same time that the clock edge is sampling the asynchronous input signal. In such a case, the resulting product may be a signal having an intermediate level that is too high to be considered a binary LOW state, and too low to be considered a binary HIGH state. The problem with an intermediate signal level is that one sampling gate could consider it a HIGH state, while another sampling gate could, at the same time, consider it a LOW state. On the other hand, the resulting product may be a signal that is too brief in duration to provide sufficient set-up time for sampling gates within a flip-flop or similar cross coupled device to properly respond. Both the intermediate signal and the brief signal are known to cause metastable oscillation if they are applied to a flip-flop or similar cross coupled device.
The usual solution to a metastable oscillation is to follow a first flip-flop with a second flip-flop in a dual stage circuit, e.g. a master-slave combination. In such a combination, the output data from the first flip-flop is transferred to the second flip-flop after a predetermined time delay which allows any metastable oscillation to die out to a valid data state within the master flip-flop before the data is switched to the slave flip-flop. However, the predetermined time delay of the usual data synchronizer is limited to a specific clock and data frequency for specific fabrication processes, and can become a bottleneck to higher frequency asynchronous data rates and higher frequency clock rates. Thus, there is a need for a data synchronizer that may be integrated using CMOS, TTL, LSTTL, etc. which synchronizes asynchronous data at higher clock and data rates for its respective fabrication process.
It is an object of the present invention to provide a data synchronizer that is substantially less sensitive to metastable oscillation.
It is another object of the invention to provide a data synchronizer that operates at a high clock frequencies and high asynchronous data rates without metastable oscillations.